• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a method for storing a counter in at least two pages of non-volatile memory (3), comprising: a step (43) for initializing a page (P0, P1, PN) with an initial value , then at each update of the counter value, a step (45) for storing an update value and an operating code (OPi) associated with this value, chosen from a set of operating codes, the current value of the counter being given by applying successive updating operations to the initial value of the page.
    公开号:FR3020712A1
    申请号:FR1453938
    申请日:2014-04-30
    公开日:2015-11-06
    发明作者:Keer Ronny Van；Guillaume Docquier
    申请人:Proton World International NV；
    IPC主号:
    专利说明:

    [0001] B13378 - 13-ZV2-1130 1 BI-DIRECTIONAL COUNTER IN FLASH MEMORY FIELD This description relates generally to electronic circuits and, more particularly, to circuits using a flash memory. The present description aims more particularly at producing a counter whose value is stored in a flash memory or in an EEPROM type memory. BACKGROUND OF THE PRIOR ART In many applications, there is a need to store the result of a meter nonvolatile so that it is kept independent of the power supply of the circuit. This is particularly the case in microcircuit cards that incorporate a microprocessor and at least one non-volatile memory, and more generally in any electronic circuit requiring counting elements in non-volatile memory. Summary Following the development of flash type memories, it would be desirable to be able to use these memories to store the counter values.
    [0002] Furthermore, it would be desirable to have a counter in non-volatile memory (flash or EEPROM) that can be incremented and decremented.
    [0003] Thus, an embodiment provides a method of storing a counter in at least two pages of nonvolatile memory, comprising: a step of initializing a page with an initial value; then, at each update of the counter value, a step of storing an update value and an operating code associated with this value, chosen from a set of operating codes, the current value of the counter being given by applying successive update operations to the initial value of the page. According to one embodiment, when a page is full, its final value is calculated and then stored as the initial value of the next page. According to one embodiment, the method comprises an initial step in which all the memory pages intended for the counter are initialized in a first state. According to one embodiment, the operating codes comprise at least one code among the addition and the subtraction. According to one embodiment, the operating codes comprise an erasure code of an entire page of the memory. According to one embodiment, the operating codes 25 include an erase code of the previous operation. According to one embodiment, a page comprises 32, 64, 128, 256, 512, 1024 or 2048 bytes. One embodiment provides a flash memory, programmed according to the above method. One embodiment provides an electronic circuit comprising such a flash memory. BRIEF DESCRIPTION OF THE DRAWINGS These features and advantages, as well as others, will be set forth in detail in the following description of particular embodiments given in a nonlimiting manner in connection with the accompanying figures among which: FIG. 1 is a block diagram of an example of an electronic circuit of the type to which the embodiments which will be described will be applied; FIG. 2 very schematically illustrates, in the form of blocks, an example of a system operating an NFC router; Figure 3 is a schematic representation of an exemplary flash memory; and FIG. 4 illustrates an embodiment of the method for programming a counter in a flash memory. DETAILED DESCRIPTION The same elements have been designated by the same references in the various figures. For the sake of clarity, only the steps and elements useful for understanding the embodiments that will be described have been shown and will be detailed. In particular, the electrical operation of a flash memory or EEPROM during the steps of writing, reading and erasing have not been detailed, the described embodiments being compatible with the usual technologies of flash memory and EEPROM . In addition, the applications using the update of a counter to be stored in a flash memory or EEPROM have also not been detailed, the embodiments described being, again, compatible with the usual applications. Using a non-volatile memory to store a counter is problematic when it is desired to minimize the number of erase steps. Traditionally, when a counter is stored in an EEPROM, programming and erasing is done by byte or by word in the memory, which provides sufficient granularity.
    [0004] B13378 - 13-ZV2-1130 4 On the one hand, it would be desirable to minimize the number of erasures to increase the lifetime of the memory. On the other hand, such operation is incompatible with a flash memory. A flash memory is programmed from an initial state to states 0 (non-conductive states of the cells). This means that the cells of the memory must be initialized to a high state and that, in order to store data, one chooses either not to intervene on the state of the bit, or to program this bit to 0. An EEPROM memory is similarly program but from an initial state to states 1. Note that the reference to a state 1 or a state 0 15 is a pure convention to designate memory points respectively loaded or unloaded. Furthermore, an erase (reset to the initial state) is necessarily made per memory page. A page is defined as the minimum size that can be addressed simultaneously for erasure. In practice, this corresponds to the size of a register receiving the serial data for transferring them in parallel to the memory plane for storage. Typically, a page currently represents, in a flash memory, 32, 64, 128, 256, 512, 1024 or 2048 bytes. However, a counter requires changing the state of a single bit (or a few bits depending on the step of increment / decrement). Whether in a flash memory or in an EEPROM, the erasing operation of a page is relatively long (typically of the order of a few milliseconds) as compared to a one-byte programming operation (typically of the order of ten microseconds). A process of clearing the page to program the new counter state at each increment would take too much time. In particular, in many applications, the time available for writing to non-volatile memory is limited. This is particularly the case in applications using near-field communication (NFC) technology because the duration of the transaction between two communicating elements 5 is only temporary and risks at any given time. to be interrupted. However, the use of a counter in non-volatile memory is, in these applications, often related to security issues in terms of access to certain information. The reliability of the meter is critical. It may be necessary to implement so-called atomicity procedures to improve this reliability. However, these procedures further increase the need for updating information in nonvolatile memory. FIG. 1 represents, schematically, in the form of blocks, an example of an electronic circuit 1 of the type to which the embodiments which will be described apply. Such a circuit comprises a processing unit 12 (PU) capable of communicating, via one or more data buses 13, addresses and commands, with different elements among which, for example, an interface of input / output 14 (I / O) of communication with the outside of the circuit 1, one or more volatile or nonvolatile memories 15 (MEM), one or more functions (symbolized by a block 16, FCT) related to the application , and at least one flash memory 3 (FLASH) or EEPROM in which it is desired to store a counter. Other elements may be connected to the buses 13 and / or be included in the circuit. If necessary, the memory 3 is external to the circuit 1. It will subsequently take the example of a flash memory to store the counter. However, the techniques that will be described also apply to the management of a counter stored in EEPROM memory, although the write and erase operations do not necessarily have the same granularity. FIG. 2 is a schematic representation of an exemplary device 2 including one or more electronic circuits 1 'forming a near field communication (NFC) communication router (NFC) capable of communicating by different buses 13 with the rest of the device 2. The NFC router serves as an interface between the different elements of the device 2 and a near-field communication antenna 22 with a neighboring device not shown. In the example of Figure 2, the NFC circuit includes at least one flash memory 3. The applications covered by this description exploit at least one counter whose value is stored in this flash memory.
    [0005] FIG. 3 very schematically illustrates an exemplary architecture of a flash memory 3, such a memory is generally organized in blocks 32 (BLOCK) each comprising several pages 34 (PAGE), each of a given number of bytes, for example 512, 1024 or 2048 bytes. The writing of DATA data in the memory 3 or erasure is effected via an input register 36 (REG). The data is typically sent in a serial communication, or byte, in the write register 36 which is then discharged in parallel to a block of the memory. In reading, the addressing of a zone also leads to the reading of a page through an output register 38 which provides the data read outside. The representation of FIG. 3 is schematic and the various control and addressing circuits have not been illustrated. Normal use of flash memory to store data smaller than the page would take too much time. Indeed, with each new value to be stored in the counter, it would be necessary to delete the entire page 30 to reprogram a new value. In the embodiments to be described, it is expected to assign several pages (at least two) to the counter and to initialize these pages by erasing them (filling them with states 1, or FF in hexadecimal notation). Then, instead of storing the value of the counter in the memory, provision is made to store an initial value of the counter followed by a series of increment or decrement values and the operations which are performed on them. are associated. Thus, the control circuit of the counter (the processing unit 12) manages at least one and preferably four operating codes for operating the counter in non-volatile memory. These four operating codes are: - No operation (optional): this operation amounts to canceling the just preceding operation; 10 - Addition: this operation consists of incrementing the counter value of the operand associated with the operating code; Subtraction: this operation consists in decrementing the counter value of the operand associated with the operating code; and - Erase (optional): this operation amounts to erasing an entire page (set it to 1 (FF) entirely). When writing the counter, that is to say an increment or decrement, the processing unit managing the counter writes, in the memory, an operating code and an operand associated with this code. When reading the value of the counter, the processing unit reads the initial value of the page stored in the first word of this page, as well as the various operations (operating codes and operands) stored in the active page. When a page is full, the next page is initialized by storing as initial value the result of the previous page (initial value updated by all 30 operations of the page). Thus, the processing unit does not need to recalculate at each reading all pages to get the current value of the counter, but only the current page. This takes advantage of fast byte writing and the relatively long erasure steps (relative to a write operation) are reserved when the entire page is full. We also take advantage of the fact that a flash memory is read anyway by full page. Therefore, it is not detrimental to have to read an entire page to calculate the current value of the meter. FIG. 4 very schematically illustrates one embodiment of a method for updating a counter in a flash memory.
    [0006] In a phase of initialization of the counter, we start by initializing (block 41, INIT PAGES) all the pages assigned to the counter. This initialization corresponds to filling all the bits in state 1. In FIG. 4, the content of the bytes has been noted in hexadecimal. Thus, in the example of FIG. 4, each line has 8 bytes. Preferably, four bytes are assigned to each update operation of the counter (operating code and operand). Once the pages have been initialized, the first page is initialized (block 43, INIT PAGE 0) by storing this initial value in its first address. For example, this initialization is at a value of zero 00 and the first four bytes of the page are written to O. The counter is then ready to be used.
    [0007] In a first operation of updating the counter value, the processing unit sends an operation (block 45, OPERATION) representing the increment or the decrement to be assigned to the counter. The OPi operation code corresponding to this operation as well as its operand (V1) are stored at the following address in the first page PO of the memory. Depending on the applications, the processing unit may or may not cause, before writing, reading of the current value of the counter. During the lifetime of the counter, update operations (block 45, OPERATION) are executed successively and B13378 -13-ZV2-1130 9 fill as and when the first page of the memory (for example V2, OPi, Vn, OPi). When the PO page is full, at the next write, the control unit starts by calculating (block 47, COMPUTE) the current value of the counter from the initial value (00) and the n stored update operations in the page P0. This value VAL is then stored as an initial value in the following page P1 (block 43 ', INIT PAGE 1). Subsequently, update operations are performed from this value VAL. Thus, it is not necessary to recalculate all the contents of the counter since the origin, but simply of the current page. Preferably, once a page is full and its final value has been transferred as an initial value on the next page, the page is erased, i.e. all of its bits are set to 1. One advantage is that it helps protect the meter by erasing its history. Thus, one page can be reused by the counter when another page is full. For example, in a simplified embodiment, the counter uses only two pages and alternates from one page to another. Depending on the nature of the meter, it uses one or more of the four possible operating codes. For example, for a single increasing counter, the subtraction operation code is not used. Conversely, for a counter only decreasing, the initial value is FF and the addition operation code is not used. However, according to a preferred embodiment, the counter is increasing and decreasing. This is one of the advantages of the described technique of incrementing and decrementing the same counter in nonvolatile memory. The optional no operation code is to cancel the previous operation. For example, if a row operation iia increments the counter by 3 and the next operation B13378 - 13-ZV2-1130 10 wishes to decrement it by 3, instead of storing the two successive operations of increment and Decrement, cancel the increment operation. For this, the memory area storing the increment operation is canceled (set to 0). The line is lost but we used one line instead of two. Such an operation serves, for example, in a protection counter against attacks of an integrated circuit where the counter is generally incremented before the function to be monitored, and then decremented by the same value at the end of the function if no attack occurs. has been detected. The choice of the size of the pages conditions the time necessary to calculate the value of the counter (time necessary to calculate the operations since the beginning of the page). An advantage of the embodiments that have been described is that they make it possible to use a flash memory to store the value of a counter. Another advantage is that the updating of the counter is fast especially with respect to the time required to erase a page in a flash memory (or EEPROM).
    [0008] Various embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, the practical implementation of the embodiments that have been described is within the abilities of those skilled in the art based on the functional indications given above and using circuits that are in themselves usual. In particular, the organization of the addressing of the non-volatile memory and the generation of the signals adapted to its control and this addressing makes use of techniques that are in themselves usual.
    权利要求:
    Claims (9)
    [0001]
    REVENDICATIONS1. Method for storing a counter in at least two pages of nonvolatile memory (3), comprising: a step (43, 43 ') of initializing a page (P0, P1, PN) with an initial value, then each update of the counter value, a step (45) for storing an update value (V) and an operating code (OPi) associated with this value, chosen from a set of operating codes the current value of the counter being given by applying successive update operations to the initial value of the page.
    [0002]
    2. The method of claim 1, wherein when a page (P0) is full, its final value is calculated and stored as initial value (VAL) of the next page (P1). 15
    [0003]
    3. Method according to claim 1 or 2, comprising an initial step (41) in which all the memory pages intended for the counter are initialized in a first state.
    [0004]
    4. The method according to any one of claims 1 to 3, wherein the operating codes comprise at least one code among addition and subtraction.
    [0005]
    5. Method according to any one of claims 1 to 4, wherein the operating codes comprise an erase code of an entire page of the memory.
    [0006]
    The method of any one of claims 1 to 5, wherein the operation codes include an erase code from the previous operation.
    [0007]
    The method of any one of claims 1 to 6, wherein a page has 32, 64, 128, 256, 512, 1024 or 2048 bytes. 30
    [0008]
    Flash memory, programmed according to the method according to any one of claims 1 to 7.
    [0009]
    An electronic circuit comprising a flash memory (3) according to claim 8.
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US20070189082A1|2006-02-16|2007-08-16|Standard Microsystems Corporation|Method for implementing a counter in a memory with increased memory efficiency|
    US20090313418A1|2008-06-11|2009-12-17|International Business Machines Corporation|Using asymmetric memory|
    US5724540A|1988-03-28|1998-03-03|Hitachi, Ltd.|Memory system having a column address counter and a page address counter|
    US20040193835A1|2003-03-31|2004-09-30|Patrick Devaney|Table lookup instruction for processors using tables in local memory|
    EP1884955A1|2006-07-28|2008-02-06|STMicroelectronics S.r.l.|Address counter for nonvolatile memory device|
    EP2108163A1|2007-01-05|2009-10-14|Proton World International N.V.|Protection of information contained in an electronic circuit|
    US8239612B2|2007-09-27|2012-08-07|Tdk Corporation|Memory controller, flash memory system with memory controller, and control method of flash memory|
    US8195973B2|2008-04-14|2012-06-05|Dell Products, Lp|Method to implement a monotonic counter with reduced flash part wear|
    US8489814B2|2009-06-23|2013-07-16|Mediatek, Inc.|Cache controller, method for controlling the cache controller, and computing system comprising the same|
    JP2012104200A|2010-11-11|2012-05-31|Renesas Electronics Corp|Data processor, nonvolatile memory, and method of determining data erase count of nonvolatile memory|
    US8873304B2|2012-09-24|2014-10-28|Infineon Technologies Ag|Integrated circuitry, chip, method for testing a memory device, method for manufacturing an integrated circuit and method for manufacturing a chip|
    FR3012655B1|2013-10-25|2015-12-25|Proton World Int Nv|FLASH MEMORY COUNTER|
    FR3020712B1|2014-04-30|2017-09-01|Proton World Int Nv|BIDIRECTIONAL COUNTER IN FLASH MEMORY|FR3020712B1|2014-04-30|2017-09-01|Proton World Int Nv|BIDIRECTIONAL COUNTER IN FLASH MEMORY|
    FR3051590A1|2016-05-20|2017-11-24|Proton World Int Nv|FLASH MEMORY COUNTER|
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    US10318416B2|2017-05-18|2019-06-11|Nxp B.V.|Method and system for implementing a non-volatile counter using non-volatile memory|
    CN107678977B|2017-09-30|2021-01-05|北京智芯微电子科技有限公司|Reading and writing method and device of counter|
    CN110634524A|2018-06-25|2019-12-31|北京兆易创新科技股份有限公司|Nonvolatile memory erasing method and device|
    US11086705B2|2019-03-18|2021-08-10|International Business Machines Corporation|Managing the reliability of pages in non-volatile random access memory|
    法律状态:
    2015-03-19| PLFP| Fee payment|Year of fee payment: 2 |
    2015-11-06| PLSC| Search report ready|Effective date: 20151106 |
    2016-03-23| PLFP| Fee payment|Year of fee payment: 3 |
    2016-04-01| CA| Change of address|Effective date: 20160301 |
    2017-03-22| PLFP| Fee payment|Year of fee payment: 4 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1453938A|FR3020712B1|2014-04-30|2014-04-30|BIDIRECTIONAL COUNTER IN FLASH MEMORY|FR1453938A| FR3020712B1|2014-04-30|2014-04-30|BIDIRECTIONAL COUNTER IN FLASH MEMORY|
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    CN201520231201.2U| CN206301593U|2014-04-30|2015-04-16|For the device and system of bidirectional counter|
    US15/243,359| US9870316B2|2014-04-30|2016-08-22|Bidirectional counter in a flash memory|
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